The present invention relates to semiconductor memory devices. More particularly, the invention relates to a pipe latch circuit that receives input data from the cell area, latches the data, and outputs the data as output to external circuitry.
In general, a synchronous memory device requires a pipe latch circuit for continuous data output. A pipe latch circuit stores the data received from the cell area and sequentially outputs them according to the synchronization signals from a clock. A pipe latch circuit controller is used to control this pipe latch circuit. A pipe latch circuit controller is a device that provides control for sequentially storing the data received from the cell area according to the synchronization signals from a clock and outputting them.
FIG. 1 is a block diagram of a typical DDR (Double Data Rate) Synchronous memory device.
In FIG. 1, the DDR Synchronous memory device comprises a row address input 400 for receiving, decoding and outputting row addresses, a column address input 300 for receiving, decoding, and outputting column addresses, a cell area 500 for outputting data according to the signals from the row address input 400 and column address input 300, an instruction interpreter 600 for receiving and decoding clock signals and instruction signals, a pipe latch circuit 100 for sequentially receiving data output from the cell area 500 and outputting to the output buffer, a pipe latch circuit controller 200 for controlling the pipe latch circuit 100 according to the signals received from the instruction interpreter 600 and the clock, and an output buffer 700 for receiving and outputting the outputs from the pipe latch circuit 100 as output data to external circuits.
In DDR memory devices where data is outputted on rising edges as well as falling edges, the pipe latch circuit receives even-numbered data and odd-numbered data from the cell area 500 separately, and sends them to the output buffer 700 as rising edge data and falling edge data, respectively. The even-numbered data and odd-numbered data are received from the cell area 500 by the pipe latch circuit 100, and outputted in synchronization with the rising edges and falling edges of external clock signals.
Meanwhile, the pipe latch circuit 100 comprises a plurality of registers whose number depend on the number of data to be received and latched, and the CAS latency of the memory device. Also, there are serial pipe latch circuits which use registers in series, and parallel pipe circuits which use registers in parallel.
FIG. 2A is a block diagram of a parallel pipe latch circuit comprising registers in parallel, according to the prior art.
With reference to the FIG. 2A, the pipe latch circuit 100a comprises a plurality of registers connected in parallel 100a for receiving even-numbered data, a plurality of registers connected in parallel 20xe2x80x2_1, 20xe2x80x2_2, . . . , 20xe2x80x2_n for receiving odd-numbered data, a plurality of path circuits 10_1, 10_2, . . . , 10_n provided at the stage preceding the registers 20_1, 20_2, . . . , 20_n, 20xe2x80x2_1, 20xe2x80x2_2, . . . , 20xe2x80x2_n for storing the received even-numbered data into the registers 20_1, 20_2, . . . , 20_n in response to n even-numbered input control signals (1xcx9cn), a plurality of path circuits 10xe2x80x2_1, 10xe2x80x2_2, . . . , 10xe2x80x2_n provided at the stage preceding the registers 20_1, 20_2, . . . , 20_n, 20xe2x80x2_1, 20xe2x80x2_2, . . . , 20xe2x80x2_n for storing the received even-numbered data into the registers 20xe2x80x2_1, 20xe2x80x2_2, . . . , 20xe2x80x2_n in response to n odd-numbered input control signals 1xcx9cn, n multiplexers 30_1xcx9c30_n for selectively outputting even-numbered data and odd-numbered data from each register 20_1, 20_2, . . . , 20_n, 20xe2x80x2_1, 20xe2x80x2_2, . . . , 20xe2x80x2_n, 2n path circuits 40_1, 40_2, 40_n, 40xe2x80x2_1, 40xe2x80x2_2, . . . , 40xe2x80x2_n provided at the output stages of the multiplexers 30_1xcx9c30_n for outputting data from the multiplexers 30_1xcx9c30_n as rising edge data or falling edge data.
FIG. 2B is a block diagram of a pipe latch circuit controller 200a for the pipe latch circuit 100a shown on FIG. 2A.
In FIG. 2B, the pipe latch circuit controller 200a receives clock signals and data output timing control signals, and outputs 2n output control signals and n multiplexer selection signals. The 2n control signals include n control signals for even-numbered data, and n control signals for odd-numbered data.
In the following, the operation of a parallel pipe latch circuit is explained with reference to FIG. 2A and FIG. 2B.
First, when the data from the corresponding read addresses are sent from the cell area to the pipe latch circuit 100a, the 2n path circuits 10_1, 10_2, . . . , 10_n, 10xe2x80x2_1, 10xe2x80x2_2, . . . , 10xe2x80x2_n are sequentially turned on, in response to the n even-numbered input control signals 1xcx9cn and n odd-numbered input control signals 1xcx9cn. As the path circuits are turned on, the even-numbered data and odd-numbered signals are sequentially stored in the registers 20_1, 20_2, . . . , 20_n, 20xe2x80x2_1, 20xe2x80x2_2, . . . , 20xe2x80x2_n.
Subsequently, the n multiplexers 30_1, 30_2, . . . , 30_n output data from the registers 20_1, 20_2, . . . , 20_n, 20xe2x80x2_1, 20xe2x80x2_2, . . . , 20xe2x80x2_n as rising edge data or falling edge data selectively.
Subsequently, the n odd-numbered output control signals (1xcx9cn) and n even-numbered output control signals (1xcx9cn) from the pipe latch circuit controller (200a) selectively turn on the path circuits 40_1, 40_2, . . . , 40_n, 40xe2x80x2_1, 40xe2x80x2_2, . . . , 40xe2x80x2_n, causing the output data from the n multiplexers 1xcx9cn passed to the output buffer (ref. 700 FIG. 1).
The above described parallel pipe latch circuit 100a has the advantage of outputting data in high speed, because input data is latched only once and outputted in response to the output control signals. However, the parallel pipe latch circuit 200a has a disadvantage in that the pipe latch circuit controller 200a becomes complex because it has to generate and output input control signals and output control signals separately.
For example, if we implement the pipe latch circuit using 16 registers, the controller is required to generate 16 input control signals (8 for even-numbered input control signals and 8 for odd-numbered input control signals) and 16 output control signals (8 for even-numbered output control signals and 8 for odd-numbered output control signals) each with different timing. Also, in this case, the parallel pipe latch circuit requires 8 multiplexers. The multiplexers require large footprint, so a parallel pipe latch circuit having a plurality of multiplexers requires large sized integrated circuit chip.
In order to solve the problem, a serial pipe latch circuit consisting of a plurality of registers connected in series is sometimes used because of its smaller footprint and simpler control structure.
FIG. 3 is a block diagram of a serial pipe latch circuit 100b consisting of registers connected in series and a pipe latch circuit controller 200b. 
In FIG. 3, the serial pipe latch circuit 100b comprises
a plurality of registers 50_1, 50_2, . . . , 50_n connected in series for receiving even-numbered data and delivering them sequentially, a plurality of path circuits 60_1, . . . , 60_nxe2x88x921 provided between the registers 50_1, 50_2, . . . , 50_n for delivering the data to the registers at the next stage, a plurality of registers 50xe2x80x2_1, 50xe2x80x2_2, . . . , 50xe2x80x2_n connected in series for receiving odd-numbered data and delivering them sequentially, a plurality of path circuits 60xe2x80x2_1, . . . , 60xe2x80x2_nxe2x88x921 provided between the registers 50xe2x80x2_1, 50xe2x80x2_2, . . . , 50xe2x80x2_n for delivering the data to the registers at the next stage, and a multiplexer 60a for selectively outputting the data stored in the nth registers 50_n, 50xe2x80x2_n as rising edge data and falling edge data.
Also, the pipe latch circuit controller 200b receives clock signals and data output timing control signals, and outputs 2(nxe2x88x921) input and output control signals, an output control signal, and a multiplexer selection signal.
The following is a description for the operation of serial pipe latch circuit 100b, with reference to FIG. 3.
First, when the addresses are given, the corresponding even-numbered data and odd-numbered data are sequentially read from the cell area into the pipe latch circuit 100b, and sequentially stored in the even-numbered data registers 50_1, 50_2, . . . , 50_n and the odd-numbered data registers 50xe2x80x2_1, 50xe2x80x2_2, . . . , 50xe2x80x2_n. At this time the pipe latch circuit controller 200b outputs nxe2x88x921 even-numbered input/output control signals 1xcx9cnxe2x88x921 and nxe2x88x921 odd-numbered input/output control signals 1xcx9cnxe2x88x921 to turn on path circuits 60_1, 60_2, . . . , 60_nxe2x88x921, 60xe2x80x2_1, 60xe2x80x2_2, . . . , 60xe2x80x2_nxe2x88x921 sequentially, so that even-numbered data and odd-numbered data are sequentially stored in the registers 50_1, 50_2, . . . , 50_n, 50xe2x80x2_1, 50xe2x80x2_2, . . . , 50xe2x80x2_n.
Subsequently, in response to the selection signals from the pipe latch circuit controller 200b to the multiplexer 60a, the data stored in the registers at the final stages 50_n, 50xe2x80x2_n are selected as rising edge data and falling edge data, and are outputted to the output buffer (ref. 700 in FIG. 1) in response to the output control signals.
Compared to the parallel pipe latch circuit, the serial pipe latch circuit has the advantage of simpler pipe latch circuit controller because the data input to the registers and the data output are controlled by the input/output signals at the same time.
As an example, a serial pipe latch circuit 100b using 16 registers will require only 14 input/output control signals. A parallel pipe latch circuit 100a requires a total of 40 control signals (16 input control signals, 16 output control signals, and 8 multiplexer control signals), while the serial pipe latch circuit requires only 16 control signals (14 input/output control signals, 1 selection signal, 1 output control signal). Therefore, the serial pipe latch circuit 100b has the advantage of simpler control than the parallel pipe latch circuit 100a. 
Also, since the serial pipe latch circuit 100b requries only one multiplexer at the final output registers, it has the advantage of far smaller footprint compared to the parallelpipe latch circuit 100a. Because the multiplexers require larger footprint than registers, with less multiplexers, the circuitry footprint is greatly reduced.
However, the serial pipe latch circuit 100b has a considerable limitation in high speed data output because the registers are connected in series from the input to the output, and are sequentially controlled. That is, only when the currently stored data is passed to the next stage register, can a new data be received.
In conclusion, the serial pipe latch circuit 100b is advantageous because of the smaller footprint in the integrated circuitry and simpler control signal generation method, but is very limited in high speed operation. Therefore, as high speed operation of memory devices are more and more in demand, there is a necessity for a pipe latch circuit that has a simple control method and at the same time can operate in high speed.
It is, therefore, an objective of the present invention to provide a pipe latch circuit with simpler control, smaller footprint, and higher speed operation.
In accordance with an aspect of the present invention, there is provided a pipe latch circuit for storing a sequentially received plurality of first data and second data and outputting them as rising edge output data or falling edge output data, including: a first input register for receiving the first data; a plurality of first serial pipe latches comprising a plurality of registers connected in series, for selectively storing the outputs from the first input registers and selectively outputting them; a first linkage register for storing the data outputted from the plurality of first serial pipe latches; a second input register for receiving the second data; a plurality of second serial pipe latches comprising a plurality of registers connected in series, for selectively storing the outputs from the second input registers and selectively outputting them; a second linkage register for storing the data outputted from the plurality of second serial pipe latches; a multiplexer for selecting the data stored in the first linkage register and the second linkage register as the rising edge output data and the falling edge output data, and outputting them; and a pipe latch circuit controller for controlling the plurality of first and second serial pipe latches and the multiplexer.